The realization of the surface code for topological error correction is an essential step towards a universal quantum computer. For single-atom qubits in silicon, the need to control and read out qubits synchronously and in parallel requires the formation of a two-dimensional array of qubits with control electrodes patterned above and below this qubit layer. This vertical three-dimensional device architecture requires the ability to pattern dopants in multiple, vertically separated planes of the silicon crystal with nanometre precision interlayer alignment. Additionally, the dopants must not diffuse or segregate during the silicon encapsulation. Critical components of this architecture—such as nanowires, single-atom transistors and single-electron transistors–have been realized on one atomic plane by patterning phosphorus dopants in silicon using scanning tunnelling microscope hydrogen resist lithography. Here, we extend this to three dimensions and demonstrate single-shot spin read-out with 97.9% measurement fidelity of a phosphorus dopant qubit within a vertically gated single-electron transistor with <5 nm interlayer alignment accuracy. Our strategy ensures the formation of a fully crystalline transistor using just two atomic species: phosphorus and silicon.