Near-Surface Electrical Characterisation of Silicon Electronic Devices Using Focused keV-Range Ions

The demonstration of universal quantum logic operations near the fault-tolerance threshold has established ion-implanted near-surface donor atoms as a plausible platform for scalable quantum computing in silicon. The next technological step forward requires a deterministic fabrication method to create large-scale arrays of donors, featuring a few-hundred-nanometer interdonor spacing. Here, we explore the feasibility of this approach by implanting low-energy ions into silicon devices featuring a $60\times 60\mu m^2$ sensitive area and an ultrathin 3.2-nm gate oxide—capable of hosting large-scale donor arrays. We employ a characterization system consisting of a modified focused-ion-beam machine and ultralow-noise ion-detection electronics to demonstrate a method for evaluating the device response characteristics to shallowly implanted 12-keV ${}^{}$$H$${}_2^{+}$ ions. Despite the weak internal electric field, near-unity charge-collection efficiency is obtained from the entire sensitive area. This can be explained by the critical role that the thermal gate oxide plays in the ion-detection response, allowing an initial rapid diffusion of ion-induced charge away from the implant site. Next, we adapt our approach to perform deterministic implantation of a few thousand 24-keV ${}^{}$$\mathrm{Ar}$${}^{}$ ions into a predefined microvolume, without any additional collimation. Despite the reduced ionization from the heavier ion species, a fluence-independent detection confidence of $\ge 99.99$% is obtained. Our system thus represents not only a method for mapping the near-surface electrical landscape of electronic devices but also a framework toward mask-free prototyping of large-scale donor arrays in silicon.