Layout-Aware Embedding of Quantum-Dot Cellular Automata Networks onto a D-Wave Quantum Annealer

Advancements in Quantum-dot Cellular Automata (QCA) fabrication have posed this technology as an alternative to CMOS for general-purpose computing. Reliable simulation of QCA circuits requires computation of the ground state and dynamics of the complete quantum mechanical formulation, which becomes computationally infeasible with increasing problem sizes. In this paper, we present an embedding algorithm which maps a QCA circuit to a D-Wave Quantum Annealing Processor to allow for efficient ground state computation. Unlike previous embedding algorithms, ours uses spatial information available in the QCA design to guide the embedding. The algorithm has two parts: a layout-aware global placement of QCA cells over the Quantum Annealer hardware grid, and a negotiated-congestion router that resolves a minor-embedding of the QCA graph on the Quantum Annealer graph. Although we present our mapping algorithm in the context of QCA, it could be applied to any quantum annealing problem instance in which spatial information is made available.