Gate-based Readout: Optimization and Scaling
November 22, 2018 @ 10:30 am
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In the quest for scaling up silicon-based quantum computing, readout by already existing gate electrodes has gained prominence due to its reduced impact in the qubit layout and comparable sensitivities to conventional charge sensors. Gate-based sensing enables readout of spins by projective measurements using the state-dependent differential capacitance of the system . Recently, single-shot readout has been achieved with this technique [2-4] but further improvements are necessary to set gate-based readout well above quantum error-correction thresholds.
In this talk, I will present results that highlight the steps to optimize gate-based readout. At the device level, the dispersive signal can be enhanced by increasing the gate-coupling to the quantum system using for example high-k dielectrics and 3D thin SOI technology . At the resonator level, a high loaded quality factor and good matching to the line are essential. These can be achieved by using superconducting elements and optimal circuit topologies [6,7]. Ultimately, at the electronics level, the sensitivity could be further improved by reducing the noise floor using quantum-limited Josephson parametric amplification.
Last, I will explain how gate-based readout can be combined with digital technology to read multiple quantum devices sequentially while reducing the number of input lines per qubit. I will show results on digitally-interfaced dynamic readout of transistor-based silicon quantum devices .
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